The present invention generally relates to a data transport control apparatus and, in particular, relates to one such data transport control apparatus having means for minimizing intraapparatus communication.
Throughout present data communication systems, data transport controllers are used which are severely limited in their data traffic handling capabilities and flexibility. Such controllers may, or may not, be in communication with other such controllers. Typically, a data transport controller includes a microprocessor connected to one or more communication peripheral devices, e.g. a synchronous communication controller, and a direct memory access (hereinafter abbreviated DMA) controller. The DMA controller and the communication device are usually connected directly to the bus of the microprocessor.
In order to transmit or receive data on such a system, the communication device is programmed with the information neccessary to effect the transfer, and the DMA controller is programmed with location information about the local source or destination of the data. As the communication device becomes ready to receive or transmit a piece of data, it signals to the DMA controller. In response, the DMA controller makes a request to the microprocessor for temporary control of the bus thereof. When the microprocessor completes its present task use of the bus is granted to the DMA controller which then generates the necessary control and address signals to effect the transfer of the requested piece of data from/to the memory of the microprocessor to/from the communication device.
When the data transfer transaction is completed, which may require the transfer of many pieces of data, an interrupt signal is generated by either the DMA controller or the communication device and presented to the microprocessor to indicate this condition. If, for example, the operation was a transmit operation, nothing more is required until another data transfer. However, if the operation was a receive operation, the microprocessor must, to prevent loss of subsequent data, re-program the DMA controller and the communication device before the next incoming data transfer is initiated. Since the microprocessor has no control as to when data will arrive, the requisite response time thereof is determined by external factors.
Problems can occur in several areas of the aforementioned scenario. For example, when the lengths of the data transfers are short and/or consecutive transfers are closely spaced, the rate of interrupts to the microprocessor can become quite frequent. This reduces the microprocessor's ability to respond, since, for every interrupt, a certain amount of inherent processing is required. Further, because the microprocessor becomes heavily occupied with the immediate problem of a heavy interrupt load, it has less time available for other tasks. In extreme cases, the microprocessor has more interrupts to service than it is able to handle, and is thus no longer able to maintain the receiving devices in a ready state to receive. As a consequence, incoming data is lost. Such a condition is especially true when a large number of communication devices is connected to a single microprocessor. In addition, since the DMA controller steals time away from the microprocessor in order to transfer a piece of data to, or from, the communication device, the time available to the microprocessor for both normal processing and interrupt processing is further diminished by the very act of data transfer. Again, when high transfer rate devices and/or a large number of devices are operating, the microprocessor bus becomes a bottleneck, due to being heavily shared. It is possible for the sum of all bus access requirements to exceed the total bus availability since there are presently no direct mechanisms to prevent same. Finally, because the microprocessor is intimately involved with each and every data transfer operation, the amount of computation, per unit of time, required of the microprocessor can easily exceed the computational capability thereof.
Conventional communication devices are generally specific to a preselected application, and have a command and control format reflecting that specific application. Further, such devices can require frequent, and, in some instances, almost continuous interaction with the microprocessor to effect the transfer of data between its local memory and the communication medium. As a consequence of the application specific nature of such communication devices, it is often necessary to copy and reformat data when transferring between dissimilar communication devices, thereby placing an additional computational load on the microprocessor.
In light of the above a data transport controller is clearly needed that reduces the interaction between the microprocessor and the devices interfacing therewith, as well as separates the data transport microprocessor program storage memory from the packet data buffer memory such that packets being transferred do not impact the performance of said microprocessor. In addition, it is highly desirable to reduce the frequency of external interrupts, i.e. due to the transfer of data to thus provide the highest possible data transfer by detaching the microprocessor from the minute command and control functions associated with external devices.